Facilities
CMOSIS facilities are located in Antwerpen, Belgium. The more than 1000 m2 infrastructure includes offices, clean room, test and characterization laboratories. CMOSIS performs wafer tests and final device tests in the 100 m2 cleanroom. Wafer tests can be performed on 8” and 12” wafers.
CMOSIS operates a state-of-the-art design environment with best-in-class tools. Installed are:
- Schematic entry, simulation front-end and IC layout tools from Cadence Design Systems
- Analog, digital and mixed signal simulation with Mentor Graphics AdvanceMS
- High-capacity simulation capabilities with Mentor Graphics ADiT turbo
- RTL-to-GDSII with Cadence Encounter
- Hierarchical verification (DRC, LVS) and extraction with Mentor Graphics Calibre
- Solid Edge for IC package design
